As is known, present nonvolatile memories, particularly flash-EEPROMs, involve complex functions, e.g., for erasing, which are performed by means for a sequencer implemented by a state machine and connected to a signal interpreter. The functions to be performed involve various count operations which, to avoid an excessive increase in the number of states and complexity of the state machine, cannot be performed directly by the sequencer. For this purpose, counters or counter elements external to the sequencer are provided--one for each count function--as well as a decoder for detecting an end-of-count value and generating a signal for the state machine.
At present, the decoder is formed using single- or multilevel static CMOS logic. The single-level logic solution features an n-input (NAND or NOR) circuit for each n-bit counter or counter element, and requires, for each circuit, n N-channel and n P-channel transistors, which creates serious layout difficulties in that a solution suitable for one type of transistor (e.g., series connection) is unsuitable for the other. Moreover, the above solution is cumbersome, and further layout problems are posed by the bus resulting from the possibly large number of supply wires required for the inputs of each circuit. Also, the efficiency of the above known solution is increasingly impaired alongside an increase in the number of inputs of each circuit. To solve this problem, a multilevel logic solution may be employed featuring circuits with a small number of inputs and output-connected to other circuits. Such a solution, however, has the disadvantage of creating multiple signal levels and greatly increasing the size and complexity of the decoder.
Moreover, each count function may comprise different end-of-count values, depending upon the current state of the operations sequencer. For example, the count function relative to the number of modification pulses to be applied to the memory cells may present two different end-of-count values for the program pulses ("byte write") and the erase pulses ("sector erase"). For each end-of-count signal, the state machine therefore evolves differently. As the number of count functions and end-of-count values for each count function increases, an increasing number of inputs are required on the state machine for receiving a specific end-of-count signal, which is of course a disadvantage.